(a) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular, to a method for fabricating a semiconductor having salicide that is capable of reducing contact resistance and sheet resistance so as to improve signal speed of a product.
(b) Description of the Related Art
Typically, in the case of selectively forming a salicide region for maintaining a signal speed of a semiconductor device, even though the transistor at the logic core region is formed to below 0.25 μm by means of a salicide process, a non-salicide process is needed at the input/output terminal regions requiring an ESD protection circuit.
In this case, non-salicide regions are formed at a diffuse layer between the source/drain contact, and salicide regions are formed on other regions (contact regions) of the diffuse layer and on the gate electrode for decreasing resistances (contact resistance at the diffuse layer and sheet resistance at the gate), in general.
Also, among nonvolatile devices such as a flat cell-type mask ROM or an EEPROM, various techniques using the BN+ (Buried N+) diffused layer as the source/drain layer at memory cell regions before the gate formation process are used. In addition, in a SOC trend in which memory and logic processes are implemented in a single chip, such nonvolatile devices may be implemented on the basis of the logic process which typically includes a salicide process.
FIGS. 2A to 2F are drawings illustrating processes for fabricating a semiconductor device having salicide according to a conventional method.
As shown in FIG. 2A, a silicon dioxide substance and electrode substance (i.e., polycrystalline silicon) are sequentially deposited on a p-type semiconductor substrate.
Next, an etching mask is formed by depositing a photosensitive substance on the electrode substance and forming an etching mask with a photolithography process in order for the photosensitive substance to be selectively left at the areas on the gate electrode to be formed. The electrode substance and silicon dioxide substance are selectively etched out with the etching mask such that the gate silicon dioxide 204 and the gate electrode 206 are formed on the semiconductor substrate 202 in a predetermined pattern.
Here, reference numeral A denotes a region on which the salicide layer is to be formed through following processes, and reference numeral B denotes a non-salicide region.
Next, as shown in FIG. 2B, a buffer layer 208, such as a silicon dioxide layer, is formed on the semiconductor after the gate electrode 206 is formed. Sequentially, a low concentration impurity region 210 is formed on the semiconductor substrate 202 by injecting a low concentration of n-type dopant ions using the gate electrode as a mask and performing the drive-in. Next, as shown in FIG. 2C, a spacer 212 is formed on a side wall of the gate electrode 206 by forming a thin film substance (silicon dioxide or nitride film) on the semiconductor substrate including the gate electrode 206 and etching back the thin film substance.
At this time, an upper surface of the gate electrode 206 and the low concentration impurity region 210 on which the spacer 212 is not coated are exposed. Also, a source/drain 214 is formed by injecting an impurity using the gate electrode and the spacer 212 as the mask.
Next, as shown in FIGS. 2D and 2E, a thin layer for suppressing a formation of the salicide at the non-salicide region B so as to distinguish the salicide region A and the non-salicide region B is formed.
In more detail, a photosensitive layer 218 is selectively formed only on the non-salicide region B through the photolithography process after forming the salicide suppression substance (nitride film or silicon dioxide) on the whole surface of the semiconductor substrate 202.
Consequently, the salicide suppression layer 216 is selectively formed only on the non-salicide region B by removing the residual photosensitive film after removing the salicide suppression substance at the region (salicide region A) on which the photosensitive film 218 is not formed, by performing a wet or dry etching process using the photosensitive film 218 as the mask.
Next, as shown in FIG. 2F, a metal substance is formed on the entire surface of the semiconductor substrate 202, and then the metal substance on the salicide region A is salicided by performing a thermal annealing process under predetermined process conditions.
In more detail, the metal substance formed on the salicide suppression layer 216 (i.e., the metal substance formed on the non-salicide region B) is kept as it was, and on the other hand, the metal substance formed on the silicon (i.e., the metal substance formed on the salicide region A) reacts with the silicon so as to be salicided. That is, the salicide is formed on the upper surface of the gate electrode 205 and the upper surface of the low concentration impurity region 210.
Finally, the metal substance on the non-salicide region B is removed through a metal substance removal process such that the semiconductor device having the salicide is completely manufactured.
In the conventional method for fabricating semiconductor devices having salicide, the photosensitive layer is selectively formed on the non-salicide region(s) B for forming the salicide suppression layer 216 on the non-salicide region B, and then the salicide suppression substance formed on the salicide region A is removed through a wet or dry etching process. However, the conventional method has a drawback in that undercuts occur to the side of the spacer 212 by the chemical used for the wet etching, for example the undercuts 220a and 220b shown in FIG. 2D, resulting in degradation of the reliability of the semiconductor device.
Also, in the case of removing the salicide suppression substance formed on the salicide region A by means of wet etching according to the conventional method, as shown in FIG. 2E, there can be a problem in that the semiconductor substrate 202 is damaged with defects 222a and 222b that are formed on the surface, resulting in degradation of the reliability of the semiconductor devices.